(Sharing haberdashery) The fundamental difference between push-pull output and open-drain output circuit in MCU output mode.
Open drain output: The output terminal is equivalent to triode collector. A pull-up resistor is required to obtain a high-level state. It is suitable for current control, and its current absorption capacity is relatively strong (usually within 20mA).
The push-pull structure usually means that two triodes are controlled respectively by two additional signals, and one triode is always on when other is off. First, let's talk about open-collector output structure. The structure of open collector output is shown in Figure 1. The collector of transistor on right is not connected to anything, so it is called an open collector (the transistor on left is used for inverting, so when input is "0", output is also "0"). In Figure 1, when input at left end is "0", front triode is disabled (that is, collector C and emitter E are disabled), so a 5V supply is added to right triode via 1K. resistor, and right triode is on (that is, switch is closed); when input at left end is "1", front triode is on and back triode is off (equivalent to a switch off).
We've simplified pic. 1 to fig. 2. The switch in Figure 2 is software controlled and is open in position "1" and closed in position "0". It can be clearly seen that when switch is closed, output is directly grounded, so output level is 0. When switch is turned off, output terminal is suspended, that is, it is in a high impedance state. At present, level status is unknown. If a resistive load (even a very light one) is connected to ground, output terminal level will be lowered by load, so this circuit cannot output a high level. Look at Figure 3 again. Resistor with a nominal value of 1 kOhm in fig. 3 is a pull-up resistor. If switch is closed, there will be a current flow through 1 kΩ resistor, but since switch is closed, other three ports have internal pull-ups), when we want to use input function, we only need to set output port to 1, which is sufficient because switch off, and for port P0 it is in a high impedance state. For an open drain (OD) output, this is very similar to an open collector output. Simply replace above triode with a field effect lamp. So collector becomes a sink and OC becomes an OD, and principle of analysis is same. Another output structure is push-pull output. The push-pull output structure is to replace top pull-up resistor with a switch. When a high level is to be output, top switch is on and bottom switch is off, and when output is to be low, opposite is true. Compared with OC or OD, this push-pull structure has strong high and low level control capabilities. If two output ports with different output levels are connected together, a large current will be generated, which may burn out output port. The OC or OD output mentioned above will not have this situation because current provided by pull-up resistor is relatively small. If a push-pull output is to be set to a high impedance state, two switches must be turned off at same time (or a transmit gate is used on output port) so that it can be used as an input state. Some I/O ports of AVR microcontroller are structured like this.
Characteristics and applications of open drain circuits
We often encounter concepts of open drain and open collector in circuit design. The "drain" referred to in concept of so-called open-drain circuit refers to drain of a MOSFET. Similarly, "set" in an open-collector circuit refers to triode's collector. An open drain circuit refers to a circuit that uses drain of a MOSFET as an output. A common use is to add a pull-up resistor to an off-drain circuit. A complete open drain circuit should consist ofopen-drain pull-up resistor and an open-drain pull-up resistor. As shown in picture 1:
The open drain circuit has following characteristics:1. Use drive capability of an external circuit to reduce drive inside IC (or drive a load that exceeds IC's supply voltage). When IC's internal MOSFET is turned on, drive current flows from external VCC through resistor R, and MOSFET goes to GND. Inside IC, only very low gate drive current is required. Figure 1. 2. Multiple open-drain output contacts can be connected to one line. Form relation "logic AND". As shown in Figure 1, when any of PIN_A, PIN_B, and PIN_C goes low, logic on open-drain line is 0. This is also principle for I2C, SMBus, and other buses to judge bus busy status. If it is used as an output, a pull-up resistor must be connected. When connected to a capacitive load, fall-off delay is a transistor in chip that is actively driven, and speed is higher; growth retardation is a passive external resistor, and speed is slower. If high speed is required, resistance selection should be small and power consumption will be large. Therefore, when choosing a load resistance, both power consumption and speed should be taken into account. 3. You can change transmit level by changing voltage of pull-up power supply. As shown in fig. 2, logic level of chip is determined by supply voltage Vcc1, and output high level is determined by supply voltage of load resistor Vcc2. This way we can control output of high level logic with low level logic (so you can do arbitrary level conversion). (For example, a TTL/CMOS level output can be obtained by adding a terminating resistor.)
4. If open-drain pin is not connected to an external pull-up resistor, it can only output a low level (so, for P0 port of classic single-chip microcomputer 51, an external pull-up resistor must be added to perform input and output functions, otherwise high logic level cannot be withdrawn). Generally speaking, open drain is used to connect devices with different levels and is used to match levels. 5. Standard open-drain contacts usually only have an output capability. Only by adding other judgment schemas can it be able to have bidirectional input and output. 6. The normal CMOS output stage has two top and bottom tubes, remove top tube to get OPEN Drain. The main purpose of this output is twofold: level shifting, linear I. 7. The linear AND function is mainly used when there are multiple nets to pull down same signal. If circuit does not want to pull down, it will output a high level because OPEN-DRAIN is off, high level is achieved by an external pull-up resistor. (In a conventional CMOS output stage, if one output is high and other is low, this is equivalent to a short circuit in power supply.)8. OPEN-DRAIN provides flexible output methods, but it also has its weakness, i.e. it has a rising edge delay. Because rising edge charges load through an external pull-up passive resistor, so when resistance is chosen small, delay will be small, but power consumption will be large; otherwise, delay will be large and power consumption will be small. Therefore, if a delay is required, it is recommended to use a falling edge output.
Pay attention to application:
1. The principles of operation with open drain and open collector are similar. In many applications, we use open collector circuits instead of open drain circuits. For example, an input pin must be driven by an open drain circuit. Then our general control method is to use a triode to form an open collector circuit to drive it, which is convenient and economical. Figure 3.
2. The pull-up resistor value R determines speed of logic level conversion edge. The larger resistance value, lower speed and lower power consumption. vice versa. Push-Pull output is so-called push-pull output, it should be more suitable for CMOS circuit than CMOS output, because push-pull output power in CMOS cannot be made as big as bipolar. The output power depends on output pole area of the N-tube and P-tube inside IC. Compared with open-drain output, push-pull high and low levels are determined by IC power supply, and logic operations cannot be performed simply. Push-pull is most widely used method for designing output stages in CMOS circuits. Of course, open drain is not without cost, that is, output driving ability is very poor. It is not correct to say that output drive power is bad and drive power depends on final power of transistor in IC. OD only brings a rising edge delay because rising edge charges load through an external pull-up passive resistor. When resistance is chosen low, delay is small but power consumption is large, otherwise delay is large and power consumption is small. OPEN DRAIN provides a flexible output method, but comes at a cost. If there is a delay requirement, it is recommended to use a falling edge output. A prerequisite for low resistance and low latency is that resistor selection principle must be within allowable power consumption range of final transistor. Experienced designers will not select a 1 ohm resistor as upper limit when using a logic chip pull-down resistor. On rising edge of pulse, power supply charges load through a passive pull-up resistor. Obviously, lower resistance, shorter rise time. On falling edge of pulse, in addition to discharging load through active transistor, power supply also passes through pull-up resistor, and turned-on transistor forms a path to ground, which causes problem of power consumption and power consumption of chip. The resistor affects rising edge, not falling edge. If you don't care about rising edge in use, pull-up resistor can be chosen as large as possible to reduce current in ground path. If requirements for rise time are high, choice of resistor size should be based on power consumed by chip.
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