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Common Mistakes of Electronics Engineers


Myth 1. Cost savings

Common mistake #1.What color should I choose for bar indicator? Personally, I like blue better, just choose it.

A positive decision. Red, green, yellow and orange indicator lights available on market, regardless of size (less than 5 mm) or packaging, last for decades, so price is usually cheap. Less than 5 cents. However, blue light indicator has only been invented in past three or four years, and technology maturity and supply stability are relatively low, so price is four or five times higher. If there are no special requirements for color of panel stack indicator you are designing, do not select blue. At present, blue indicator light is usually used only in cases where other colors cannot be changed, such as when displaying video signals.

Common Mistake 2. It doesn't seem to matter what resistance value you use for these pull-up/pull-up resistors, just pick an integer of 5K.

Yes: There is actually no resistance value of 5K on market, nearest value is 4.99K (1% accuracy), followed by 5.1K (5% accuracy), cost price is 4 times higher than accuracy and 2 times higher than 4.7k by 20%. 20% precision resistors only have resistance values ​​of 1, 1.5, 2.2, 3.3, 4.7 and 6.8 (including integer multiples of 10), respectively, 20% precision capacitors also only have above values . For resistors and capacitors, if you choose values ​​other than these, you must use higher precision and cost will be doubled. If precision requirements are not high, it is expensive to do so. In addition, quality of resistors is also very important. Sometimes a batch of poor quality resistors is enough to ruin a project. It is recommended to buy original products from shopping malls such as EasyMart.

Common Mistake #3: This logic can be built with 74XX gate diagrams, but it's too simple, so let's use CPLD, which looks much more high tech.

Positive decision: 74XX gate circuit costs only a few cents and CPLD costs at least tens of dollars (GAL/PAL only costs a few dollars, but this is not recommended), and cost has increased significantly Not to mention already about fact that it also adds several times to work of production, documentation, etc. Assuming this won't affect performance, it's obviously more worthwhile to use more economical 74XX.

Common Mistakes of Electronics Engineers

Common Mistake 4. The PCB design requirements for this board are low, so use a thinner line and lay it out automatically.

Positive decision: automatic routing will inevitably take up more PCB area and at same time create many times more vias than manual routing. Important factors are width and number of vias, which respectively affect output of PCB and consumption of drills. In addition, area of ​​the PCB is also an aspect that affects price. Therefore, automatic layout inevitably increases cost of PCB production.

Common Mistake 5. Our system requirements are so high that all chips including MEM, CPU, FPGA, etc. should be chosen as fastest.

Good solution: In a high-speed system, not every part runs at high speed, and each time speed of device increases by one level, cost will almost double, and it will also bring signal integrity problems Big negative impact. Therefore, when choosing a chip, one should consider degree of use of different parts of device, and not use of fastest one.

Common Mistake #6. As long as program is stable, longer code and lower efficiency are not key factors.

Yes: CPU speed and memory can be bought with money. If you spend a few more days making program more efficient when writing code, you can reduce CPU frequency and memory footprint. The power is definitely worth it. The CPLD/FPGA design is also similar.

Myth 2. Reliable design

Common Mistake #7. This board was produced in small batches and no problems were found after extensive testing, so there is no need to read chip manual.

A positive decision. The hardware design and application of chip must comply with relevant specifications, especially all parameters specified in chip manual (withstanding voltage, I / O level range, current, time, temperature, PCB layout, power quality, etc.) must be strictly match settings and cannot be verified experimentally alone. Many companies have experienced painful lessons in many products. Products have been on sale for a year or two, and chip manufacturers have changed production line, and boards will not be transferred. The reason is that parameters of their chips have changed a little, but they are not beyond manual. If you take manual as a standard, then no changes are scary. If parameters go beyond scope of manual, then you can ask him for compensation (if your board can still spin at that time,then your reliability will be even better).

Common mistake #8: User error. If there's a problem, I can't be blamed.

Positive Decision: It is right to require users to act strictly according to guidelines, but users are people too and sometimes they will make mistakes. key, it will fail, or if you put in wrong plug, you will burn board. . Therefore, various errors that users may make must be predicted and protected in advance.

Common Mistake 9. The reason this card is broken is because card at other end has a problem and it's not my responsibility.

Positive decision: There must be sufficient compatibility with various external hardware interfaces, and you cannot completely disconnect because signal of other side is abnormal. If it is not normal, it should only affect part of function associated with it, while other functions should work fine and should not be completely damaged or even permanently damaged, and after restoring interface, you should also return to normal immediately.

Common Mistake 10. As long as this part of scheme requires that software be designed this way, there will be no problem.

A positive decision. Many of device's hardware features are directly controlled by software, but software often has bugs and it's impossible to predict what will happen after program has finished running. The developer must ensure that no matter what software does to hardware, irreversible damage does not occur within a short period of time.

Myth three: system efficiency

Common Mistake 11. Do you use interrupts or requests for so many tasks? Let's break early.

A positive decision. The interrupt happens in real time, but not necessarily fast. If there are too many interrupted tasks, if this one does not complete, then it will follow one after another, and system will crash after a while. If number of tasks is large but very frequent, a lot of CPU power is wasted in overhead of entering and exiting interrupts, and system efficiency is extremely low. If request method is used instead, efficiency can be greatly improved, but request sometimes cannot meet requirements of real time, so best way is to request in an interrupt, that is, after entering interrupt, all accumulated tasks are processed and then exit.

Common Mistake 12: A 100MB CPU can only handle 70%, but a 200MB CPU is fine.

A positive decision. ProcessingThe carrying capacity of system depends on many factors. In communications business, memory is usually bottleneck. No matter how fast processor is, it's useless if external access can't be accelerated.

Common Mistake 13. If CPU uses a larger cache, it should run faster.

A positive decision. Increasing amount of cache memory does not necessarily improve system performance. In some cases, closing cache is faster than using cache. The reason is that data moved to cache needs to be reused many times to improve system efficiency. Therefore, in a communication system, typically only instruction cache is enabled, and even if data cache is enabled, it is limited to a portion of storage space, such as a portion of stack. At same time, when designing a program, it is also necessary to take into account capacity and size of cache block, which includes length of key code cycle body and transition range. CACHE and it loops all time, that would be problematic.

Common Mistake 14. Memory interface timing is a manufacturer default configuration and should not need to be changed.

Favourable decision: The default BSP value for memory interface is set to most conservative setting. In practical applications, it should be adjusted reasonably in combination with parameters such as bus operating frequency and Timeout period. Sometimes reducing frequency can improve efficiency. For example, RAM access cycle is 70ns, and when bus frequency is 40M, set access time to 3 cycles, that is, 75ns, if bus frequency is 50M, then it should be set to 4 cycles, actual access time is reduced to 80ns.

Common Mistake #15: This CPU has a DMA and must be fast to move data with it.

Good solution: real DMA is to start devices on both ends at same time after hardware takes over bus, and read here and there in one cycle. However, many DMAs built into CPU are just simulations. A lot of preparatory work (setting start address and length, etc.) is required before each DMA starts up. During transfer, it is often read into temporary storage on chip. first and then written, i.e. it takes two clock cycles to move data once, which is faster than moving data with software (no need to get instructions, no extra work like wraparounds), but if you only move a few bytes per time, you have to do a lot of preparatory work, as well as function calls, which is inefficient. Thus, this kind of direct memory access is only suitable for largedata blocks, don't use it blindly.

Common Mistake 16: If one CPU can't handle it, use two distributions to handle it and processing power can be doubled.

Positive solution: when moving bricks, two people should be twice as efficient as one person; when painting, one person can only do a disservice. How many CPUs to use can only be determined after a good understanding of business, i.e. cost of coordination between two CPUs should be minimized so that 1+1 is as close to 2 as possible, and should not be less than 1.

Common Mistakes of Electronics Engineers

Misconception #4: Low Power Design

Common Mistake #17: All those bus signals are wired with resistors, so I feel more relaxed.

A positive decision. There are many reasons why signals need to be raised and lowered, but not all of them need to be pulled up. The pull-up and pull-up resistor pulls a simple input signal, and current is less than tens of microamps, but when slave signal is pulled, current reaches milliamp level. The current system often has 32 bits of address data. , and maybe. If isolated 244/245 bus and other signals are pulled up, a few watts of power will be consumed by these resistors (don't use concept of 8 cents per kilowatt hour to treat a few watts of power, reason is as follows).

Common Mistake 18. Our system is powered by 220V so we don't have to worry about power consumption.

A positive decision. The low power design is not only to save energy, but also to reduce cost of power module and heat dissipation system, reduce electromagnetic radiation and thermal noise interference. By reducing temperature of device, service life of device is extended accordingly (the operating temperature of semiconductor device increases by 10 degrees, and service life is halved). Energy consumption issues must be considered at all times.

Common Mistake #19 These little ICs use little power, so don't worry about that.

Positive decision: It is difficult to determine power consumption of a chip that is not too complex inside. Basically, it is determined by current at output. ABT16244 consumes less than 1 millisecond if there is no load.An, but its performance is that each leg can drive a load of 60mA (such as resistance matching in tens of ohms), that is, maximum power consumption of a full load can reach 60 * 16 \u003d 960mA of course, only supply current is so large, heating It's all about load.

Common Mistake 20. What to do with these unused CPU and FPGA I/O ports? You can leave this field blank and talk about it later.

Positive decision: If an unused I/O port is suspended, it may become a repetitive oscillating input due to little interference from outside world and power consumption of MOS device is mainly dependent on gate circuit Number of flips. If you pull it up, there will also be microamp current on each pin, so it's best to set it up as an output (of course, no other controlled signals can be connected externally).

Common Mistake #21 This FPGA has so many gates left, let'slet's play with them.

A positive decision. The power consumption of an FPGA is proportional to number of flip-flops used and number of flips, so power consumption of same type of FPGA can vary by 100 times depending on different circuits at different times. Minimizing number of high-speed flip-flops is main way to reduce FPGA power consumption.

Common Mistake 22: There are so many control signals in memory, I only need to use OE and WE signals for this board, and chip select must be grounded so that data will come out much faster during a read operation.

A positive decision. The power consumption of most memory modules will be more than 100 times higher with chip select enabled (regardless of OE and WE) than with chip select disabled, so CS should be used. maximum possible chip control and maximum chip select pulse width reduction when other requirements are met.

Common Mistake #23: Reducing power consumption is job of hardware team, not software team.

A positive decision. The hardware is just stage, but main thing is software. Access to almost all chips on bus and inversion of each signal is almost completely controlled Software can reduce external memory accesses (more use of register variables, more use of internal cache, etc.), timely response to interrupts (interrupts are often active low level and have pull-up resistors) and other specific measures for specific boards will affect power reduction. Made a lot of contributions. If you want a board to spin well, you need to understand both hardware and software!

Common Mistake 24. Why are these signals out of range? As long as it blends well, it can be eliminated.

A positive decision. With exception of a few specific signals (such as 100BASE-T, CML), there is overshoot, if it is not too large, it does not need to be matched. , even if it matches, it's not necessarily best match. For example, TTL output impedance is less than 50 ohms, and some even 20 ohms. With such a large terminating resistor, current will be very large, power consumption will be unacceptable, and signal amplitude will be too small. In addition, output impedance of conventional signals is not same when outputting a high level and when outputting a low level, and there is also a way to achieve a perfect match. Thus, terminating TTL, LVDS, 422, and other signals is only necessary to achieve acceptable overshoot.

Myth Five: Signal Integrity

>Common Mistake #25 These signals have been simulated and should be accurate.

A positive decision. The simulation model cannot be exactly same as real thing, even real thing processed in different batches is different, not to mention model. In addition, real situation is very different and simulation cannot exhaust all possibilities, especially crosstalk. There was once a lesson that there is only a certain length of packets on a certain board, which makes it very easy to lose packets. The end reason is that value of length field is 0xFF. When this data appears on bus, it interferes with adjacent WE signal, which causes write to RAM to fail. Other data will also interfere with WE, but interference is within acceptable range. However, when 8-bit bus switches from 0 to 1 at same time, nearby signals will be overloaded. The conclusion is that simulation results are for reference only and sufficient margin should be left.

Common Mistake #26: The more decoupling capacitors, better power supply.

A positive decision. In general, more decoupling capacitors, more stable power supply will be, but too many decoupling capacitors also have disadvantages: waste of money, complex wiring, too much power. - for impulse current, etc. The key to designing decoupling capacitors is choosing right capacitance and placing them in right place. General IC manuals have references to designing decoupling capacitors. It is best to follow manual.

Common Mistake #27 Since this is a digital signal, steeper edge, better.

Positive decision: steeper edge, wider spectral range and more energy in high-frequency part; higher frequency, easier signal is emitted. (for example, a microwave station can be turned into a mobile phone, and longwave radio stations are not available in many countries), easier it is to interfere with other signals, and worse quality of one's own transmission on wire becomes. So if you can use low speed chips, try using low speed chips.

Common Mistake #28: Signal matching is really problematic. How to match it correctly?

Good solution: Generally speaking, when signal travel time on wire exceeds jump time, signal reflection becomes important. The reason for signal reflection is caused by line impedance unevenness. The purpose of matching is to make impedance of leading end, load end, and transmission line close, but whether it can match well depends on topological structure of signal line on PCB. hole, angle, socket, changedistances between different positions and ground wire, etc. change impedance and these factors will make reflected signal extremely complex, very complex. It is difficult to match, so only point-to-point methods are used for high-speed signals to minimize issues such as through holes and corners.

Common Mistake 29: Treat a 100M data bus as a high frequency signal. Since this clock is only 8K, this is not a big problem.

Good decision: The value of data bus is usually determined by a certain edge of control signal or clock signal, provided that edge is maintained with sufficient settling and hold time, is there interference or overshoot, special this will have no effect (of course, surges should not exceed maximum voltage that microcircuit can withstand), but no matter how low frequency of clock signal is (in fact, spectrum range is very wide), its edge is most critical, while it should be its monotonicity is ensured, and jump time must be within a certain range.