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Pay attention to PCB vias


Pay attention to PCB vias

Via vias are one of important components of multilayer printed circuit boards, and cost of drilling is usually between 30% and 40% of cost of manufacturing a printed circuit board. Simply put, every hole on a PCB can be called a via.

In terms of function, vias can be divided into two categories:

  • One is used as electrical connection between layers

  • Second is to fix or position device.

  • From a process point of view, these vias generally fall into three categories: blind vias, hidden vias, and through vias.

    Blind Holes

    Located on top and bottom surfaces of PCB, has a certain depth and serves to connect surface circuit and circuit of inner layer below it. The hole depth usually does not exceed a certain ratio (diaphragm).

    Buried pits

    refers to a connection hole located in inner layer of a PCB that does not open onto surface of PCB. The above two types of holes are located in inner layer of PCB. A through-hole forming process is used before lamination, and several inner layers may be overlapped during through-hole formation.

    Through hole

    This type of hole runs through entire PCB and can be used for internal interconnection or as a mounting hole for positioning components.

    Because through hole is easier to implement in process and cost is lower, most PCBs use it instead of other two types of vias. The following vias, unless otherwise noted, are considered vias.

    From a structural point of view, a via basically consists of two parts: one is drilled hole in middle, and other is pad area around drilled hole. The size of these two parts determines size of via.

    Obviously, when designing high-speed, high-density PCBs, it is always desirable to keep vias as small as possible to leave more room for wiring on board. less parasitic via capacitance, and smaller and more suitable for high-speed circuits.

    However, reducing size of hole also increases cost, and size of through hole cannot be reduced without restrictions. central position, and when hole depth exceeds 6 times diameter of drilled hole, it is not possible to ensure uniform copper coating of hole wall.

    For example, if thickness (through-hole depth) of a typical 6-layer PCB is 50 mils, then under normal conditionsx drill diameter specified by PCB manufacturer can only reach 8 mils.

    With development of laser drilling technology, size of drilled hole can also be smaller and smaller. Generally, a through hole with a diameter less than or equal to 6 mils is called a pinhole. Microvias are often used in HDI (High Density Interconnect) designs. Microvia technology allows vias to be placed directly on via-in-pads, greatly improving circuit performance and saving wiring space.

    The via hole looks like a discontinuous break point on transmission line, causing signal reflections. Typically, equivalent impedance of a via is about 12% lower than that of a transmission line. For example, a 50 Ω transmission line impedance will decrease by 6 Ω when passing through a through hole (specifically, size of through hole and board thickness, not reduced).

    But reflection caused by discontinuous through-hole impedance is actually very small, and its reflection coefficient is only:


    Problems caused by vias are more related to effects of parasitic capacitance and inductance.

    Via parasitic capacitance

    The through hole itself has parasitic capacitance with respect to ground. If it is known that insulating hole diameter of via on ground layer is D2, pad diameter is D1, PCB board thickness is T, and electrical constant of substrate is ε, then parasitic capacitance of via is approximately equal to:


    The main effect of through-hole parasitic capacitance in a circuit is to increase rise time of signal and reduce speed of circuit.

    For example, for a PCB with a thickness of 50 Mils, if a 10 Mil ID thru-hole is used with a pad diameter of 20 Mils, and distance between pad and ground copper is 32 Mils, then we can use above formula to approximate The calculated parasitic capacitance of via is approximately equal to:


    Rise time change caused by this capacitance part:

    T10-90=2.2C(Z0/2)=2.2x0.517x(55/2)=31.28 ps

    It can be seen from these values ​​that while slew-delay slowing effect caused by parasitic capacitance of a single via is not apparent if vias are used multiple times in wiring to switch between layers, EDA365 eForum reminds that design still needs to be carefully considered .

    Via parasitic inductance

    Similarly, parasitic inductance and parasitic through hole capacitance. When designingIn high-speed digital circuits, harm caused by parasitic through-hole inductance is often greater than effect of parasitic capacitance. . Its parasitic series inductance will weaken contribution of shunt capacitor and weaken filtering effect of entire power system.

    We can use following formula to simply calculate approximate parasitic via inductance:

    L=5.08 h[ln(4 h/day)+1]

    Where L refers to inductance of via, h is length of via, and d is diameter of center drilled hole. It can be seen from formula that diameter of through hole has little effect on inductance, and length of through hole affects inductance.

    Still using above example, via inductance can be calculated as:

    L=5.08x0.050[ln(4x0.050/0.010)+1]=1.015 nH

    If rise time of a signal is 1 ns, then its equivalent resistance is:

    XL=πL/T10-90=3.19 ohm

    This impedance cannot be neglected when passing high frequency current. Pay particular attention to fact that shunt capacitor must pass through two vias when connecting power layer and ground layer so that parasitic inductance of vias is multiplied.

    Due to high-speed PCB design

    From above analysis of parasitic characteristics of vias, it can be seen that in high-speed PCB design, seemingly simple vias often have a large negative impact on circuit design. following aspects can be achieved in design as much as possible:

  • Considering cost and signal quality, select a reasonable via size. For example, for 6-10-layer memory module PCB design, 10/20Mil vias (drill/pad) are better, and for some high-density and small size boards, 8/18Mil vias can be tried. , hole.

    In current specification, it is difficult to use smaller vias. For power or ground vias, consider using a larger size to reduce impedance.

  • From above two formulas, it can be concluded that using a thinner PCB is beneficial in reducing two via parasitic parameters.

  • The power and ground leads must be drilled side by side. The shorter wire between via and lead, better, as they increase inductance. In this case, power and ground leads should be as thick as possible to reduce impedance.

  • The signal traces on PCB should not change layers as much as possible, that is, minimize unnecessary vias.

  • Place someground vias next to vias where signal changes layers to provide a close signal return. even on PCB There are a lot of redundant ground vias on board. Of course, design requires flexibility.

  • The via model discussed above is case where each layer has a pad. Sometimes we can reduce or even remove pads of some layers.

  • Especially in case of a very high density of vias, this can break circuit insulation slot on copper layer. To solve this problem, in addition to moving position of via, we can also consider placing a through in pad size of copper layer is reduced.

    How to use vias: From above analysis of parasitic characteristics of vias, we can see that when designing high-speed printed circuit boards, incorrect use of seemingly simple vias often causes great harm to circuit design. negative effect.