Detailed explanation of working principle of TTL gate circuit

In hardware circuits, you can use digital devices such as logic gates. However, for such digital devices, there are basically two main branches in terms of internal structure of process, one is made up of transistors and other is made up of field devices. effects tubes. Many engineers have also heard of TTL level and CMOS level. In fact, they refer to logic gate circuits made up of these two processes. They can be easily distinguished by comparing triode and MOS tubes among commonly used switching tubes.

So let's introduce a TTL gate circuit today. In fact, there are many types of TTL gate circuits, such as NOT gates, NAND gates, OR gates, OR gates, and OC-issued NAND gates. Although there are many types, basic principle of operation is same. So, next I will introduce classic TTL NAND gate circuit. After understanding its basic principle of operation, other things will naturally be known.

As an example, let's take built-in logic element of 74LS00 chip, which consists of transistors inside. Its symbol is shown in figure below:

What does its internal structure look like? As shown below:

(Picture 1)

Let's first get familiar with these three levels: input layer, intermediate layer, and output layer.

(Picture 2)

Input stage: T1 is a multi-emitter transistor that can be thought of as a diode, as shown in fig. 2. Thus, it can be seen from figure that input stage is an AND gate circuit: Y ' = A B. Only when A and B are both 1, Y' will output 1 and rest of Y' will be 0.

Intermediate stage: consists of triode T2 and resistors R2 and R3. In process of opening circuit, amplifying effect of T2 is used to provide more base current for output tube T3, which speeds up conduction of output tube. Therefore, role of intermediate stage is to increase turn-on speed of output lamp and improve performance of circuit.

(Figure 3)

Output stage: consists of transistors T3, T4, diode D4 and resistor R4. As shown in Figure 3, Figure 3(a) is a triode NOT gate circuit, and Figure 3(b) is output stage in a TTL NAND gate circuit. It can be seen from figure that output stage implements logical NOT operation by transistor T3. However, a resistive load consisting of triode T4, diode D4 and R4 is used to replace R4 in gate circuit of NOT triode in output stage circuit, purpose is to make output stage have a large load capacity. Among them, D4 can play a protective role in reverse breakdown of be triode.

After understanding how each layer works, let's analyze its logic in relation to entire internal circuitry. The following analysis assumes that input high and low levels are 3.6V and 0.3V, respectively, and conduction voltage drop of PN junction is 0.7V.

1) All inputs A and B are high ≥ 2.0 V (logic 1)

If you do not take into account presence of T2, it should be Vb1=VA+0.7≥2.7V. Obviously, in presence of T2 and T3, emitter junctions T2 and T3 must be turned on simultaneously. Once T2 and T3 are on, Vb1 is fixed at 2.1V (Vb1 = 0.7 × 3 = 2.1V), so emitter junction of T1 is reverse biased and collector junction is forward biased, which is called inverted . operating condition of amplifier. Since power supply provides enough base potential for T2 through collector junction of R1 and T1 to saturate T2, voltage drop created by T2's emitter current across R3 provides enough base potential for T3 to saturate T3. output terminal VY = Vce_sat ≈0.3V (<0.4V) and Vce_sat is saturation voltage drop of T3.

It can be seen that one of logical functions of NAND gate is implemented: when all inputs are high, output is low.

2) Low level of any input A and B≤0.8V (logic 0)

When one or more input terminals are low (logic 0), T1 base and emitter are forward biased, emitter junction is on, and T1 base potential is fixed at Vb1=VB. +0.7≤1.5 V.

1. When Vb1≤1.4, both T2 and T3 are turned off. Since T2 is disabled, current flowing through R2 from operating VCC supply is only base current of T4. This current is small and voltage drop across R2 is small and negligible. Therefore, Vb4≈VCC = 5V, so T4 and D4 If it enabled, that is: VY=Vce=VCC-Vbe4-Ud=5-0.7-0.7=3.6V.

2. When 1.4V < Vb1≤1.5V, T2 is boosted and turned on while T3 is still off, so there will be a voltage drop across R2. At this time, Vb4 = VCC - V2, assuming V2 ≤ 1.2V, Then VY=Vce=VCC-V2-Vbe4-Ud=5-1.2-0.7-0.7≥2.4V. In fact, a gate output level ≥ 2.4 V is considered high.

You can see that another aspect of logic function of NAND gate is implemented: when input is low, output is high.

Given above two situations, circuit satisfies NAND logic function and is a NAND gate.