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One article explains how to perform high-speed PCB signal integrity simulations.


We know that when designing a PCB, a schematic diagram indicates wiring relationship of each signal. When laying, designer only needs to connect all signal lines according to connection relationships and follow physical and electrical rules of laying, and design seems complete. But as mentioned before, for design of high-speed circuit boards such as memory circuit boards, it is far from sufficient to consider only interconnection of signal connections. Rough design will not only bring signal integrity problems such as reflection and crosstalk, but also affect system timing , and in severe cases, developed product will not work properly. How to foresee and do so in order to avoid various problems in design?

In following, we will use Cadence SPECCTRAQuest for simulation analysis as an example and give you a preview of how to perform high-speed PCB process before and after simulation.

Preparation before modeling

Whether you want to pre-model or post-model, in most cases following preparation is required.

1) Get component's IBIS model

SPECCTRAQuest, like any other circuit analysis software, must provide accurate electrical models of circuit components in order to obtain accurate simulation results. These models may be provided by component manufacturer, or designer may formulate them in correct format according to test results under certain conditions. As a rule, we cannot know test results of components, so we need to obtain models provided by component manufacturers.

Typically in SPECCTRAQuest we use IBIS component model. It should be clear that if any component of same type or another type supplied by different manufacturers is selected, IBIS model corresponding to this component must be found. If chosen model is incorrect, any subsequent analysis and modeling becomes meaningless. In some unavoidable situations, such as IBIS model corresponding to a certain component cannot be found, we can use a similar component model for simulation to get approximate simulation results. However, we can only make sure that similar models in most cases can receive similar waveforms, but we cannot exclude possibility of dissimilar waveforms.

Of course, for components that should not participate in simulation or whose functions we are not interested in, such as EEPROM in a memory module, there is no need to consider its IBIS model. Chapter 7 of Part 1 provides several websites for downloading some of common IBIS models.

2) Preoformat IBIS file and import model

Go to SPECCTRAQuest and open ".brd" file for analysis. Although SPECCTRAQuest modeling tool does not directly read IBIS file, it can convert IBIS model to a dml format supported by calling software itself. Specific operation steps: In SPECCTRAQuest interface, click Analyze->SI/EMI Sim->Library;

In lower right corner of pop-up window, there is a "Translate" function button, click to select "ibis2signoise", select Ibis model file you want to convert in directory path, after conversion is completed, you can see corresponding file in your library view dml. If converted dml file already exists, you can also directly add corresponding dml file to directory path by clicking "Add Existing Library->".

3) Load appropriate model into component

The purpose of this step is to load each model into appropriate components. Specific steps:

a. Select model assignment in SI/EMI Sim menu;

b. The Signal Model Assignment window appears. Select a component and click "Find Model";

in. In Model Browser window that appears, select desired model. Among them, Show Model From column can select library where model is located, Model Type Fitter column can select model type, and enter "*" into model name pattern to display all models in list. selected library and type. Some components, such as passive components such as resistors and capacitors, need to create models on their own, click "Create Model" (for passive components, select Espicemodel, and for other I/O models, use IBISdevice model), and then follow instructions, to enter value and function of each pin. Yes, at same time, it can be saved to create a *.dat file so that it can be directly loaded when doing simulation in future, thus avoiding repeating above process.

4) Determine voltage of power supply

The power supply here also includes ground. Only when power supply voltage and ground level are defined can power supply model be invoked when extracting topological model. This step is optional for both front and rear simulations if signal lines required for simulation analysis are not connected to power and ground. Specific operation steps:

a. Select Logic->Identify DC Nets in SPECCTRAQuest;

b. At this time, DC Networks Identification dialog box will appear, select power signal, fill in appropriate voltage in Voltage column, and confirm (OK or Apply).

One article explains how to perform high-speed PCB signal integrity simulations.

Picture 6

5) PCB stack settings

By adjusting physical thickness of each PCB layer and linewidth of wiring layer, characteristic impedance of wiring on each PCB layer can meet design requirements to ensure accuracy of simulation results. Specific operation steps:

Choose Setup->Cross Section or SPECCTRAQuest shortcut button. The Layout Cross Section dialog box will appear. In this dialog box, you can add or remove stack layers, and change parameters such as type, material, thickness, conductivity, permittivity, line width, and characteristic impedance of each layer. Generally speaking, number and sequence of PCB stacks, as well as type, material, conductivity, dielectric constant, etc. of each layer have been determined and must be set according to given requirements. To achieve required characteristic impedance, line width (within a certain range) and dielectric thickness are usually adjusted for pre-simulation. For post-simulation, since wiring is completed, main thing that can be adjusted is dielectric thickness.

Also, when we use Cadence PSD version 14.2 to set up stack, program often crashes, which can be solved with script commands instead of manual settings.

6) Defining simulation parameters

Various simulation parameters must be set before simulation so that simulation results can more accurately reflect designer's requirements. Of course, if necessary, simulation parameters can also be adjusted during simulation analysis. Specific operation steps:

Select Analyze->SI/EMI Sim->Preferences in SPECCTRAQuest (or select Analyze->Preferences in Sigxplore);

The Analysis Perferences dialog box opens. The parameters that can be set here include device model parameters, relationship model parameters, simulation settings, units of measurement, EMI parameters, power integrity parameters, etc. The following are commonly used: number of simulation cycles (measurement cycle), clock frequency ( clock frequency), duty cycle (duty cycle), offset (offset), fixed simulation time (fixed duration), waveform sampling time (waveform resolution). ), cutoff frequency, simulation mode (FTS mode), excitation excitation (excitation excitation), measurement mode (measurement mode) and so on. As a general rule, default value can be used and everyone can make individual adjustments to suit their needs.

Post-Design Modeling Process

Because post-design simulation is more common and its execution isTo be more formulaic, I'll mention post-modeling process here.

We are currently using Cadence SPECCTRAQuest for design post-simulation, mainly for a number of signal integrity issues caused by reflections on a single PCB, and temporarily rarely consider other factors such as crosstalk, EMI, etc. .

1) Make sure all preparations are done

Generally speaking, before running a simulation, it's best to check if preparatory work has been done well. Otherwise, when simulation is halfway through, it will find that original stack is not set (still default) or which model is not set correctly. Previously done simulation is in vain, and you have to do everything all over again.

2) Select signal line

Select signal line to simulate in Signal Analysis dialog box. In fact, there are many useful functions in Signal Analysis dialog box, which will be discussed below. Specific operation steps:

a. Select AnalyzeÆSI/EMI SimÆProbe (or shortcut One article explains how to perform high-speed PCB signal integrity simulations.
), Signal Analysis dialog box appears. Fill in * in Network column so that all nets appear in left box and user can select any of signal lines to simulate. Of course, you can also click List of Nets to load an existing netlist file (a netlist file can be created by selecting Logic->Create List of Nets in SPECCTRAQuest), or click Net Bowser to select nets you want to display.

b. In driver pins, load pins, and other pins, pins of selected circuit will be displayed according to relationship between input and output. But this is not inevitable. Whether network pins can be displayed in appropriate box depends on whether pin type of device is accurate when creating circuit device package, or developer can also select Logic->Output Type in SPECCTRAQuest Edit pin type of each device in file .

3) Extract Net Topology

This is most commonly used method in our subsequent simulation. Select a target network, extract its topology, and enter Sigxplorer for analysis and simulation. Specific steps:

After selecting target network in Signal Analysis dialog box, click View Topology in lower right corner. At this time, SPECCTRAQuest enters Sigxplorer and displays extracted schema's topology template in Sigxplorer interface. Therefore, we can also use View Topology button as a bridge between SI Expert and Sigxplorer.

Verify that extracted net layout template is correct. Sometimes, for some reason we do not understand, there are models that only extract circuit components (drivers, receivers, transmission lines, etc.), but do not relate to connection of these components. My personal guess might be that via model (Via) is incomplete, or that too many arbitrary angles are used in PCB design.

In Sigxploer interface, there is a spreadsheet below circuit topology template. This spreadsheet has several columns namely Parameters, Dimensions, Results and Commands, clicking on them will display corresponding modules in table.

4) Select different excitations and component parameters to simulate

Analysis and simulation should be performed in customization environment required by designer. Sigxplorer provides various drive excitation modes, as well as detailed and comprehensive editable parameters for various components, and allows for parameter analysis. For our current post-simulation design requirements, features provided by Sigxplorer are powerful and efficient.

Concrete steps:

Press white word "TRISTATE" in second line above excitation source of this circuit, and following window will appear:

In this window, select correct excitation mode for excitation source (usually we choose Pulse as excitation type, burst excitation), and some mode parameters need to be changed in Analyze->Preferences. If you need to adjust parameters of transmission line model and some components such as resistors and capacitors in a circuit, you can click on first line of text of that component, i.e. component name, and Sigxplorer spreadsheet will automatically go to "Parameters" column and expand it to "All component parameters" as shown in figure below:

Then change value of parameter in table as desired. After setting parameters, select Analyze->Simulate or press shortcut button to run simulation. So Sigxplorer spreadsheet interface will automatically jump to "Results" column and display simulation results, and if parameter sweep simulation is not running (i.e. all parameters have a certain value), it will also automatically call SigWave to display simulation results.

5) Analysis of simulation results

For simulation results, let's take reflection analysis as an example, as shown in figure below:

The information it contains: SIM ID (number of simulations), diver (drive source), sink (sink), cycle (measurement cycle), FTS MODE (simulation mode), monotonic (monotonicity), Noise Margin (noise) . limit), overshoothigh (upper overshot), overshootlow (lower overshoot), PropDelay (transmission delay, drive end to receiver), switching delay (switching delay), settling delay (settling time), etc. In many cases, we pay more attention to resulting waveform displayed by SigWave, which can be analyzed along with waveform. The noise margin is generally required to be large enough, spikes and spikes must not exceed specified voltage, there is no obvious ringing phenomenon, waveform is not seriously distorted, and rising and falling edges of signal must be monotonic. etc. But different schemes sometimes have special requirements for length of transmission delay time or rate of rise time, which requires designer to analyze specific issues.

6) Using SigWave

The SigWave waveform display feature is to visually display simulation results (actually a spreadsheet file) as waveform diagrams. SigWave supports input of simulation results in various formats such as Hspice, Quad, etc., meanwhile, it can also save current waveform as a .sim file or output it in graphic formats such as Bitmap. , JEPG and spreadsheet text format. As for display function, SigWave is also relatively powerful and easy to use. It can be easily implemented by zooming in and out, showing and hiding waveforms, adding and removing labels, andmeasurements and notes, change display colors, etc., and provides functions such as spectrum diagram, eye diagram, and other display modes.

7) End of post-modeling

After completing network simulation in Sigxplorer, you can close Sigxplorer program and return to SI Expert. If you want to simulate a new signal and compare it with previous simulated signal waveform in same oscilloscope window, you can switch window, select a different network in SI Expert signal analysis dialog, extract it, and select Yes. when prompted, so that oscilloscope window does not close while new structure is being retrieved. But sometimes this confuses model in Sigxplorer and makes it impossible to model a new network topology template. This may be a SPECCTRAQuest bug. Before closing Sigxplorer, in order to facilitate writing of simulation reports and subsequent verification, it is usually necessary to save extracted topology template in .top file format along with waveform file in .control location graphical format.